1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device with a memory cell including a transfer transistor and a storage capacitor of a stacking type, and a fabrication method thereof.
2. Description of the Prior Art
A Dynamic Random Access Memory (DRAM) is capable of randomly reading/writing of the stored data. The DRAM usually has a lot of memory cells each having a transfer transistor and a capacitor, because of its simple structure. This structure of the memory cell has been widely used as it is optimum for higher integration of the cells.
Conventionally, with the DRAM memory cells of this sort, the storage capacitors with various three-dimensional configurations have been developed and actually used with the increasing integration scale of the cells. The purpose of the three-dimensional configurations of the capacitors is as follows:
It is essential for the storage capacitor to decrease the chip area more and more to cope with the increasing integration. To ensure the stability and reliability of the DRAM operation, the capacitor needs to have a specific minimum capacitance or greater. Therefore, it is essential for the lower electrode (i.e., storage electrode) of the capacitor to have a three-dimensional structure, thereby increasing the surface area of the capacitor without increasing the chip area.
The conventional three-dimensional configurations of the storage cell can be divided into two types;, the "stacking type" and the "trench type". These two types have merits and demerits, respectively. However, the three-dimensional configurations of the stacking type have an advantage that the memory cell has a high noise resistance property due to the .alpha.-ray and peripheral circuitry, and therefore, it is capable of stable DRAM operation even for the comparatively small capacitance. Accordingly, it has been supposed that the three-dimensional configurations of the stacking type are effectively applicable to the 1-Gbit DRAMs where the design rule of approximately 0.15 .mu.m is applied.
With the storage capacitors of the "stacking type", which are termed the "stacked capacitors", conventionally, a lot of energetic study has been performed for the cylindrical storage capacitors and various improvement has been made therefor. An example of the conventional DRAM memory cells having the stacked capacitor with the cylindrical configuration is shown in FIG. 1, in which the storage electrode is concentrically formed.
In FIG. 1, a field oxide layer 102 is selectively formed on a main surface of a p-type single-crystal silicon substrate 101, defining active regions on the substrate 101. The surface of the substrate 101 is exposed from the field oxide layer 102 in the active regions. For the sake of simplification, only one of the active regions thus defined is shown in FIG. 1
In the active region, a gate electrode 104 is formed over the substrate 101 and a gate oxide layer 103. A pair of n.sup.+ -type diffusion regions 105 and 106 are formed in the substrate 101 at each side of the gate electrode 104. The pair of diffusion regions 105 and 106, the gate oxide layer 103, and the gate electrode 104 constitute a Metal-Oxide-Semiconductor (MOS) field-Effect Transistor (FET) serving as a transfer transistor of the memory cell. The pair of diffusion regions 105 and 106 serve as a pair of source/drain regions of the MOSFET, respectively.
An interlayer insulating layer 107 is formed to cover the transfer transistor and the field oxide layer 107. A contact hole 107a is formed in the interlayer insulating layer 107 at a location just over the source/drain region 106.
A lower electrode 108 is formed on the interlayer insulating layer 107. The lower electrode 108 is contacted through the contact hole 107a with the underlying source/drain region 106 to be electrically connected to the region 106. The source/drain region 106 serves as a storage node.
A first cylindrical electrode 109, a second cylindrical electrode 110, and a third cylindrical electrode 111 are formed on the lower electrode 108. The first, second, and third cylindrical electrodes 109, 110, and 111 are contacted with and electrically connected to the lower electrode 108, respectively. These three cylindrical electrodes 109, 110, and 111 form a triple-cylindrical configuration. The three cylindrical electrodes 109, 110, and 111 and the lower electrode 108 constitute a storage electrode 112 of the capacitor.
A dielectric layer 113 is formed to cover the storage electrode 112. An upper or plate electrode 114 is formed on the dielectric layer 113.
The storage electrode 112, the dielectric layer 113, and the plate electrode 114 constitute the storage capacitor.
Thus, the conventional DRAM memory cell of FIG. 1 includes the single MOS transfer transistor and the single storage capacitor with the triple-cylindrical configuration.
With the conventional DRAM memory cell of FIG. 1, if the memory cell is further miniaturized for 256-Mbit or 1-Gbit DRAMS, the following problem will occur.
Specifically, in the fabrication process sequence of the conventional DRAM memory cell of FIG. 1, a cleaning process is necessary after the processes of forming the storage electrode 112. During this cleaning process, the cylindrical electrodes 109, 110, and 111 tend to be damaged and/or broken because of the pressure of a flowing liquid cleaner and others. Therefore, the thickness of the cylindrical electrodes 109, 110, and 111 is difficult to be further decreased, unless the satisfactorily large mechanical strength is ensured.
To further decrease the thickness of the cylindrical electrodes 109, 110, and 111 while keeping their mechanical strength at a satisfactory level, it is essential to develop some new material having an excellent step-coverage property and providing a satisfactorily low stress. However, such new material is presently quite difficult to developed. As a result, the multiple-cylindrical configuration has a limit use for further miniaturization.
As described above, since the thickness of the cylindrical electrodes 109, 110, and 111 is difficult to further decrease in the conventional the memory cell of FIG. 1, the height of the storage electrode 112 will be inevitably higher and higher to provide increasing storage capacity to cope with further miniaturization.
However, if the height of the storage electrode 112 is large, the cell array area where the memory cells of the DRAM are regularly arranged tends to have an excessively large step or height difference from the peripheral circuit area where the peripheral circuitry of the DRAM is arranged. This large height difference will cause some problems with the photo lithography process resolution is degraded and breaking and/or short-circuit occurs in interconnecting or wiring metallization.